In advanced CMOS technology, so-called local interconnects are used to increase packing density. Such a scheme involves the definition of defined conducting paths of, e.g., polysilicides, after source/drain implantation has occurred and before the deposition of an intermediate-oxide layer. It provides a means of creating buried contacts which permit a direct connection between the polysilicon layer and the active regions without a metal interconnection.
The conventional process for forming local interconnects (hereinafter referred to as "LIs") begins with standard CMOS fabrication steps. After source/drain implantation has taken place, thin layers of a heat-resistant metal, such as titanium, and alpha silicon are sputtered in the form of a double layer. The alpha silicon is then patterned by means of a photolithographic process and annealed in a nitrogen atmosphere, so that silicide will form where silicon and metal are in contact. Selective etching then removes the unconverted metal and, in the case of titanium, any titanium nitride that may have formed, and the wafer is subjected to a second annealing process in order to convert the original C49 silicide to the lower-resistivity C54 silicide. After that, the standard CMOS process is continued with silox BPSG deposition.
In these methods, aside from the formation of the LIs in a self-aligning process, source, drain, and gate regions are silicidized and, thus, made less resistive (SALICIDE process).
Particularly for small structures, the conventional method has a number of disadvantages:
The above-mentioned patterning must be performed using an anisotropic etching technique (RIE) so as to avoid underetching. This involves the risk of so-called filaments of alpha silicon being left in the gate corners, which in the further course of the process may cause short circuits by the formation of metal-silicide straps. If this is to be avoided, extreme overetching is necessary, which, in turn, has the disadvantage of removing part of the metal, so that outside the LI regions, the metal will be considerably thinner than in those regions where the local interconnects are formed. This means, however, that during the subsequent salicide formation, a) too little silicide will form on the first-mentioned regions, which thus become highly resistive, and b) too much silicide will form on the LI regions, involving the risk of interconnection failures with reverse currents. See M. G. Pitt et al., "Electrical Characterization of Submicron Titanium Silicon Local Interconnect Technology", ESSDERC 89, p. 903 et seq., where the above-mentioned problems are described in connection with the titanium-silicide formation.
The effectiveness of the removal of the alpha silicon from the gate corners by overetching depends essentially on the shape of the spacers which isolate the edges of the polysilicon gate proper. The shape of the spacers, and here particularly their side steepness, however, is subject to general process variations, so that the reliability of the filament removal is not ensured.
In addition, the silicide formation in the first annealing step is a sensitive process for the non-LI regions since it is determined by two competing reactions. If the heat-resistant metal is titanium, titanium nitride will form from the surface, and titanium silicide will form from the titanium/silicon interface. For this reason, process steps which may unintentionally affect the surface of the reactive titanium, such as the above-mentioned etching and photoresist-stripping steps in the course of the photolithographic process, are undesirable. There is the danger of the nitride formation as well as the silicide formation becoming unrepeatable due to contamination, which also includes oxidation.
It is, therefore, the object of the invention to modify the above method in such a way that it does not nave the disadvantages described. This object is attained by the invention as claimed and as described herein.